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HD74SSTV16857B
1:1 14-bit SSTL_2 Registered Buffer
REJ03D0023-0100Z (Previous ADE-205-712 (Z)) Rev.1.00 Jun.03.2003
Description
The HD74SSTV16857B is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and ) LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input. CLK RESET Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to itive CLK CLK) maintain noise margins. When RESET is low, all registers are reset and all outputs are low. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
Features
* Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input RESET RESET) * Differential SSTL_2 (Stub series terminated logic) CLK signal * Flow through architecture optimizes PCB layout * Ordering Information
Part Name HD74SSTV16857BTEL HD74SSTV16857BNEL Package Type TSSOP-48 pin TVSOP-48 pin Package Code TTP-48DBV TTP-48DEV Package Abbreviation T N Taping Abbreviation (Quantity) EL (1,000 pcs / Reel) EL (1,000 pcs / Reel)
Note: Please consult the sales office for the above package availability.
Rev.1.00, Jun.03.2003, page 1 of 16
HD74SSTV16857B
Function Table
Inputs RESET L H H H H: L: X: : : Note: CLK X L or H CLK X H or L D X H L X L H L Q0 *1 Output Q
High level Low level Immaterial Low to high transition High to low transition eady 1. Output level before the indicated steady state input conditions were established.
Rev.1.00, Jun.03.2003, page 2 of 16
HD74SSTV16857B
Pin Arrangement
Q1 1 Q2 2 GND 3 V DDQ 4 Q3 5 Q4 6 Q5 7 GND 8 V DDQ 9 Q6 10 Q7 11 V DDQ 12 GND 13 Q8 14 Q9 15 V DDQ 16 GND 17 Q10 18 Q11 19 Q12 20 V DDQ 21 GND 22 Q13 23 Q14 24
48 D1 47 D2 46 GND 45 V CC 44 D3 43 D4 42 D5 41 D6 40 D7 39 CLK 38 CLK 37 V CC 36 GND 35 V REF RESE 34 RESET 33 D8 32 D9 31 D10 30 D11 29 D12 28 V CC 27 GND 26 D13 25 D14
(Top view)
Rev.1.00, Jun.03.2003, page 3 of 16
HD74SSTV16857B
Absolute Maximum Ratings
Item Supply voltage Input voltage
*1 *1, 2
Symbol VCC or VDDQ VI VO IIK IOK IO JA Tstg
Ratings -0.5 to 3.6 -0.5 to VDDQ+0.5 -0.5 to VDDQ+0.5 50 50 50 115 -65 to +150
Unit V V V mA mA mA mA C / W C
Conditions
Output voltage
Input clamp current Output clamp current Continuous output current VCC, VDDQ or GND current / pin Package thermal impedance Storage temperature Notes:
VI < 0 or VI > VCC VO < 0 or VO > VDDQ VO = 0 to VDDQ TSSOP
ICC, IDDQ or IGND 100
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or d any other conditions beyond those indicated under "recommended operating conditions" is not der implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This current will flow only when the output is in the high state and VO > VDDQ.
Rev.1.00, Jun.03.2003, page 4 of 16
HD74SSTV16857B
Recommended Operating Conditions
Item Supply voltage Output supply voltage Reference voltage Termination voltage Input voltage AC high level input voltage AC low level input voltage DC high level input voltage DC low level input voltage High level input voltage Low level input voltage Symbol Min VCC VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VDDQ 2.3 1.15 VREF-40 mV 0 -- -- 1.7 -0.3 0.97 360 -- -- 0 Typ 2.5 2.5 1.25 VREF -- -- -- -- -- -- -- -- -- -- Max 2.7 2.7 1.35 VREF+40 mV VCC -- -- VDDQ+0.3 0.7 1.53 -- -20 20 70 Unit Conditions V V V V V V V V V V mV mA m mA C D D D D RESET RESET CLK, CLK CLK, CLK VREF = 0.5 x VDDQ
VREF+310 mV -- VREF+150 mV --
VREF-310 mV V VREF-150 mV V
Differential (Common mode range) VCMR input voltage (Minimum peak to VPP
peak input)
High level output current Low level output current Operating temperature
IOH IOL Ta
Note: The RESET input of the device must be held at VDDQ or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is low.
Rev.1.00, Jun.03.2003, page 5 of 16
HD74SSTV16857B
Logic Diagram
*1
RESET CLK CLK D1
34 38 39 48
VREF
35
1D C1 R
1
Q1
To thirteen other channels
Note:
1.
RESET input gate is connected to VDDQ.
Rev.1.00, Jun.03.2003, page 6 of 16
HD74SSTV16857B
Electrical Characteristics
Item Input diode voltage Output voltage
Symbol VCC (V)
Min -- 1.95 0 -- -- -- --
Typ -- -- -- -- -- 25 -- 38
Max -1.2 -- VDDQ 0.2 0.35 5 45 10 45
Unit Test Conditions V V IIN = -18 mA IOH = -100 A IOH = -16 mA IOL = 100 A IOL = 16 mA A mA A VIN = 2.7 V or 0 VIN = VIH(AC) or VIL(AC), IO = 0 RESET = GND
VIK VOH VOL
2.3 2.3 2.3
2.3 to 2.7 VCC-0.2 -- 2.3 to 2.7 -- 2.7
Input current
(All inputs)
IIN ICC
*2
Quiescent supply current Standby current
2.7
ICC (stdy) 2.7
*2
Dynamic operating clock only ICCD
2.7
A/ RESET = VCC, clock VI = VIH(AC) or VIL(AC), MHz CLK and CLK switching 50% duty cycle A/ clock MHz / data input pF
*4
Dynamic operating per each ICCD *2 data input
2.7
--
11
15
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle.
Output high *3 Output low
*3
rOH rOL rO() Data inputs CIN
CLK and CLK
2.3 to 2.7 7 2.3 to 2.7 7 2.5 2.5 *1 -- 2.5 2.5 --
-- -- -- -- -- 3.0
20 *4 20 4 3.5 3.5 --
IOH = -20 mA IOL = 20 mA IO = 20 mA, Ta = 25C VI = VREF310 mV
VCMR = 1.25 V, VPP = 360 mV
rOH - rOL each *3 separate bit Input capacitance
RESET Notes: 1. 2. 3. 4.
VI = VCC or GND
All typical values are at VCC = 2.5 V, Ta = 25C. Total ICC (max) = ICC + {ICCD (clock)xf(clock)} + {ICCD (Data)x1/2f(clock)x14} (clock) This is effective in the case that it did terminate by resistance. See figure. 1, 2.
Rev.1.00, Jun.03.2003, page 7 of 16
HD74SSTV16857B
Switching Characteristics
Item
*1
Symbol
VCC = 2.5 0.2 V Min Max 200 -- -- -- -- -- --
Unit
Test Condition
Clock frequency Setup time Hold time
fclock Fast slew rate Slow slew rate Fast slew rate Slow slew rate
*4, 6 *5, 6 *4, 6 *5, 6
-- 0.75 0.9 0.75 0.9 22 22
MHz ns ns ns ns Data before CLK, CLK Data after CLK, CLK Data inputs must be low after RESET high. Data and clock inputs must be held at valid levels (not floating) after RESET low. CLK, CLK "H" or "L"
tsu th tact tinact
Differential inputs active time Differential inputs inactive time
Pulse width Output slew
*3
tw tSL
2.5 1
-- 4
ns volt/ns
(CL = 30 pF, RL = 50 , VREF = VTT = VDDQ x 0.5)
Item Symbol VCC = 2.50.2 V Min Maximum clock frequency Propagation delay time
*2
Unit Max -- 2.8 5.0 MHz ns
Typ -- -- --
FROM (Input)
TO (Output)
fmax tPLH, tPHL tPHL
200 1.1 --
CLK, CLK Q RESET Q
Notes: 1. Although the clock is differential, all timing is relative to CLK going high and CLK going low. 2. This timing relationship is specified into test load (see waveforms - 3, 4) with all of the outputs lo switching. 3. Assumes into an equivalent, distributed lo to the address net structure defined in the load application information provided in this specification. 4. For data signal input slew rate 1 V/ns. 5. For data signal input slew rate 0.5 V/ns and < 1 V/ns. 6. CLK, CLK signals input slew rates are 1 V/ns.
Rev.1.00, Jun.03.2003, page 8 of 16
HD74SSTV16857B
Test Circuit
VTT
*2
50 Test point
*1
C L = 30 pF
Notes:
1. 2.
CL includes probe and jig capacitance. VTT = VREF = VDDQ x 0.5
Waveforms - 1
LVCMOS RESET Input VCC VCC /2 tinact
*1
VCC /2 0V tact 90 % 10 % I CCH I CCL
I CC
Rev.1.00, Jun.03.2003, page 9 of 16
HD74SSTV16857B Waveforms - 2
tw VIH Input VREF VREF VIL
Timing input
VCMR
VPP
tsu
th VIH
Input
VREF
VREF VIL
Waveforms - 3
Timing input
VCMR
VCMR
VPP
tPLH
tPHL V OH
Output
VTT
VTT VOL
Rev.1.00, Jun.03.2003, page 10 of 16
HD74SSTV16857B Waveforms - 4
LVCMOS RESET Input VIH VCC /2 VIL tPHL VOH Output VTT VOL
Notes:
1. 2. 3. 4. 5. 6. 7.
ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. All input pulses are supplied by generators having the following characteristics : s PRR 10 MHz, Zo = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). , The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ/2 VIH = VREF+310 mV (AC voltage levels) for differential inputs. VIH = VCC for LVCMOS input. VIL = VREF-310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. tPLH and tPHL are the same as tpd
Rev.1.00, Jun.03.2003, page 11 of 16
HD74SSTV16857B
Application Data
* Pull-down
150 120
Current (Amps)
90 60 30 0 0.0
Min Max
0.5
1.0
1.5
Voltage (V)
2.0
2.5
3.0
Figure. 1
* Pull-up
Voltage (V)
0.0 0 -30
Current (Amps)
0.5
1.0
1.5
2.0
2.5
Min Max
3.0
-60 -90 -120 -150
Figure. 2
Rev.1.00, Jun.03.2003, page 12 of 16
HD74SSTV16857B
Curve Data
Voltage (V) Pull-down I (mA) Min 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 0 8 15.5 23 29.5 35.5 41 46 51 55 58 61 63 64.5 65.5 66 66.5 67 67 67 67.5 67.5 68 68 68 68 68 68 I (mA) Max 0 12.5 24 36 47 57.5 67.5 77 86 95 103 110 116 122 126 130 132 133 134 134 134 135 135 135 135 135 135 135 Pull-up I (mA) Min 0 -8 -16 -23.5 -30.5 -37 -43.5 -49 -54.5 -59.5 -64 -67.5 -71 -73.5 -75.5 -77 -78 -79 -80 -81 -82 -83 -83.5 -84.5 -85 -86 -86.5 -87 I (mA) Max 0 -10 -21 -31 -41 -50.5 -59.5 -68 -77 -85 -92 -99.5 -106 -112 -118 -123 -127 -131 -134 -137 -139 -141 -142 -144 -145 -147 -148 -149
Rev.1.00, Jun.03.2003, page 13 of 16
HD74SSTV16857B
Package Dimensions
As of January, 2003
12.5 12.7 Max 48 25
Unit: mm
1 *0.19 0.05
0.50
24
0.08 M 8.10 0.20 0 - 8
6.10
1.0
0.65 Max
*0.15 0.05
0.10
0.10 0.05
1.20 Max
0.50 0.1
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-48DBV -- -- 0.20 g
Rev.1.00, Jun.03.2003, page 14 of 16
HD74SSTV16857B
As of January, 2003
9.70 9.90 Max 48 25
Unit: mm
1 *0.18 0.05
0.40 0.07 M
24
4.40
0.40 Max
6.40 0.20 1.00
*0.15 0.05
0.10 0.05
1.20 Max
0 - 8 0.50 0.10
0.08
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-48DEV -- -- 0.12 g
Rev.1.00, Jun.03.2003, page 15 of 16
HD74SSTV16857B
Sales Strategic Planning Div.
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Rev.1.00, Jun.03.2003, page 16 of 16

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